2784 search results - page 196 / 557 » Instruction Level Parallelism |
124
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HPCA
1997
IEEE
15 years 8 months ago
1997
IEEE
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in ...
140
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IPPS
1996
IEEE
15 years 8 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
136
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HPCA
1995
IEEE
15 years 8 months ago
1995
IEEE
In this paper we consider several hardware implementations of the general-purpose atomic primitives fetch and Φ, compare and swap, load linked, and store conditionalon large-scal...
134
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SPDP
1991
IEEE
15 years 8 months ago
1991
IEEE
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
150
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EUROPAR
2008
Springer
15 years 6 months ago
2008
Springer
Cache affinity between a process and a processor is observed when the processor cache has accumulated some amount of the process state, i.e., data or instructions. Cache affinity i...