2784 search results - page 229 / 557 » Instruction Level Parallelism |
306
Voted
ICFP
2012
ACM
13 years 6 months ago
2012
ACM
Graphics processing units (GPUs) provide both memory bandwidth and arithmetic performance far greater than that available on CPUs but, because of their Single-Instruction-Multiple...
158
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SPAA
2010
ACM
15 years 9 months ago
2010
ACM
Transactional Memory (TM) is a promising technique that simplifies parallel programming for shared-memory applications. To date, most TM systems have been designed to efficientl...
162
Voted
JSA
2010
14 years 11 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
147
Voted
IPPS
1997
IEEE
15 years 8 months ago
1997
IEEE
Tools for parallel systems today range from specification over debugging to performance analysis and more. Typically, they help the programmers of parallel algorithms from the ea...
141
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ICFP
2008
ACM
16 years 4 months ago
2008
ACM
The trend in microprocessor design toward multicore and manycore processors means that future performance gains in software will largely come from harnessing parallelism. To reali...