2784 search results - page 236 / 557 » Instruction Level Parallelism |
154
Voted
TPDS
2010
15 years 2 months ago
2010
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
143
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BMCBI
2008
15 years 4 months ago
2008
Background: The DNA microarray technology allows the measurement of expression levels of thousands of genes under tens/hundreds of different conditions. In microarray data, genes ...
146
Voted
IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not...
133
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ICASSP
2008
IEEE
15 years 10 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
119
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IPPS
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract—Many studies have shown that load imbalancing causes significant performance degradation in High Performance Computing (HPC) applications. Nowadays, Multi-Threaded (MT1...