2784 search results - page 237 / 557 » Instruction Level Parallelism |
166
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IPPS
2008
IEEE
15 years 10 months ago
2008
IEEE
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
108
Voted
MICRO
2003
IEEE
15 years 9 months ago
2003
IEEE
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a ...
141
Voted
IEEEPACT
2002
IEEE
15 years 9 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
162
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HPCA
2000
IEEE
15 years 8 months ago
2000
IEEE
Efficiency of synchronization mechanisms can limit the parallel performance of many shared-memory applications. In addition, the ever increasing performance gap between processor...
113
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HPCA
1998
IEEE
15 years 8 months ago
1998
IEEE
A novel dynamic register renaming approach is proposed in this work. The key idea of the novel scheme is to delay the allocation of physical registers until a late stage in the pi...