Sciweavers

2784 search results - page 239 / 557
» Instruction Level Parallelism
Sort
View
131
Voted
ISCAS
2006
IEEE
154views Hardware» more  ISCAS 2006»
15 years 10 months ago
FleXilicon: a reconfigurable architecture for multimedia and wireless communications
— This paper proposes a new reconfigurable architecture for multi-media and wireless communications. The proposed architecture addresses three critical design issues with the loo...
Jong-Suk Lee, Dong Sam Ha
SKG
2006
IEEE
15 years 10 months ago
Ontology Enabled Learning Resource Modeling and Management
In this paper, we proposed the learning resource ontology(LRO) models to formally describe learning content and learning context, respectively. In addition to utilizing the models...
Zongkai Yang, Tao Huang, Qingtang Liu, Xia Li, Bei...
135
Voted
PDCAT
2005
Springer
15 years 9 months ago
Gracefully Degrading Battery-Aware Static Multiprocessor Schedules Based on Symmetric Task Fusion
A novel strategy for employing schedules obtained using standard static scheduling algorithms in a battery powered multiprocessor environment is investigated. The strategy is able...
Frode Eika Sandnes, Oliver Sinnen, Yo-Ping Huang
131
Voted
CLADE
2003
IEEE
15 years 9 months ago
G-Monitor: A Web Portal for Monitoring and Steering Application Execution on Global Grids
As Grids are emerging as the next-generation computing platform, the need for Web-based portals that hide low level details of accessing Grid services for deployment and execution ...
Martin Placek, Rajkumar Buyya
139
Voted
IEEEPACT
2002
IEEE
15 years 9 months ago
Speculative Alias Analysis for Executable Code
Optimizations performed at link time or directly applied to final program executables have received increased attention in recent years. Such low-level optimizations can benefit...
Manel Fernández, Roger Espasa