2784 search results - page 241 / 557 » Instruction Level Parallelism |
141
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APCSAC
2005
IEEE
15 years 9 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
143
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ASPLOS
2004
ACM
15 years 9 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
135
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PLDI
2000
ACM
15 years 8 months ago
2000
ACM
We describe the design and implementation of Dynamo, a software dynamic optimization system that is capable of transparently improving the performance of a native instruction stre...
113
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ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
The trace cache is a recently proposed solution to achieving high instruction fetch bandwidth by buffering and reusing dynamic instruction traces. This work presents a new block-b...
153
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DSN
2007
IEEE
15 years 8 months ago
2007
IEEE
Although there are various ways to exploit software vulnerabilities for malicious attacks, the attacks always result in unexpected behavior in program execution, deviating from wh...