2784 search results - page 242 / 557 » Instruction Level Parallelism |
151
Voted
CGO
2004
IEEE
15 years 7 months ago
2004
IEEE
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...
138
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COMPUTER
2002
15 years 3 months ago
2002
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
126
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ICPP
2009
IEEE
15 years 10 months ago
2009
IEEE
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
145
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CASES
2004
ACM
15 years 9 months ago
2004
ACM
This paper presents and reports on a VLIW code compression technique based on vector Hamming distances [19]. It investigates the appropriate selection of dictionary vectors such t...
127
Voted
HPCA
1999
IEEE
15 years 8 months ago
1999
IEEE
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...