2784 search results - page 245 / 557 » Instruction Level Parallelism |
140
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DAGSTUHL
2004
15 years 5 months ago
2004
Abstract. This paper introduces a set of design principles that aim to make processor architectures amenable to static timing analysis. Based on these principles, we give a design ...
116
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GRAPHICSINTERFACE
2000
15 years 5 months ago
2000
We describe a 3D graphical interaction tool called an amplification widget that allows a user to control the position or orientation of an object at multiple scales. Fine and coar...
131
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JDS
2007
15 years 4 months ago
2007
Operational Risk management, the least covered component of Enterprise Wide Risk Management, needs intelligent tools to implement Comprehensive Emergency Management Programs. In t...
148
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FAC
2000
15 years 3 months ago
2000
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...
130
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HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
A path confidence estimate indicates the likelihood that the processor is currently fetching correct path instructions. Accurate path confidence prediction is critical for applica...