2784 search results - page 246 / 557 » Instruction Level Parallelism |
152
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HPCA
2007
IEEE
16 years 4 months ago
2007
IEEE
If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Althou...
151
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HIPEAC
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. Threads experiencing long-latency loads on a simultaneous multithreading (SMT) processor may clog shared processor resources without making forward progress, thereby star...
136
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MICRO
2008
IEEE
15 years 10 months ago
2008
IEEE
— Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed arch...
102
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CGO
2006
IEEE
15 years 10 months ago
2006
IEEE
Explicit Data Graph Execution (EDGE) architectures offer the possibility of high instruction-level parallelism with energy efficiency. In EDGE architectures, the compiler breaks ...
165
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ICS
2004
Tsinghua U.
15 years 9 months ago
2004
Tsinghua U.
Studying program behavior is a central component in architectural designs. In this paper, we study and exploit one aspect of program behavior, the behavior repetition, to expedite...