2784 search results - page 248 / 557 » Instruction Level Parallelism |
104
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CGO
2008
IEEE
15 years 10 months ago
2008
IEEE
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
142
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ASAP
2006
IEEE
15 years 10 months ago
2006
IEEE
An increasing computational demand is placed on the image processing capacity of current and future smart cameras. SIMD processor architectures provide an efficient solution becau...
129
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CODES
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
141
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
116
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SCOPES
2004
Springer
15 years 9 months ago
2004
Springer
Digital signal processing applications are implemented in embedded systems with fixed-point arithmetic to minimize the cost and the power consumption. To reduce the application ti...