2784 search results - page 254 / 557 » Instruction Level Parallelism |
160
Voted
HPDC
2012
IEEE
13 years 6 months ago
2012
IEEE
This paper presents a scheme to optimize the mapping of HPC applications to a set of hybrid dedicated and cloud resources. First, we characterize application performance on dedica...
136
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ICPP
2009
IEEE
15 years 10 months ago
2009
IEEE
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...
231
Voted
WETICE
1997
IEEE
15 years 8 months ago
1997
IEEE
Contemporary product design and process development is based on an iterative specify-evaluate-revise approach which is often time intensive and therein non-responsive to customer ...
128
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SAMOS
2009
Springer
15 years 10 months ago
2009
Springer
We believe that future many-core architectures should support a simple and scalable way to execute many threads that are generated by parallel programs. A good candidate to impleme...
145
Voted
ASPLOS
2006
ACM
15 years 10 months ago
2006
ACM
Exploiting thread level parallelism is paramount in the multi-core era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded progra...