2784 search results - page 257 / 557 » Instruction Level Parallelism |
143
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CASES
2005
ACM
15 years 6 months ago
2005
ACM
Computer security becomes increasingly important with continual growth of the number of interconnected computing platforms. Moreover, as capabilities of embedded processors increa...
232
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ISCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
125
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DSD
2009
IEEE
15 years 10 months ago
2009
IEEE
— In this paper, we present a novel framework for the automated generation of Network-on-Chips (NoC) architectures, that enables architecture exploration and optimization. The au...
136
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ROMAN
2007
IEEE
15 years 10 months ago
2007
IEEE
—Teaching a robot new skills may require that the teacher scaffolds the teaching experience appropriately. However, due to inherent assumptions made by a human teacher the scaffo...
116
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...