2784 search results - page 260 / 557 » Instruction Level Parallelism |
145
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ICCD
2006
IEEE
16 years 28 days ago
2006
IEEE
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
144
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ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
Memory latency tolerant architectures support thousands of in-flight instructions without scaling cyclecritical processor resources, and thousands of useful instructions can compl...
149
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ICS
2003
Tsinghua U.
15 years 9 months ago
2003
Tsinghua U.
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
128
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ICS
2001
Tsinghua U.
15 years 8 months ago
2001
Tsinghua U.
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
147
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IEEEPACT
1998
IEEE
15 years 8 months ago
1998
IEEE
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...