For some sequential loops, existing techniques that form speculative threads only at their loop boundaries do not adequately expose the speculative parallelism inherent in them. T...
Lin Gao 0002, Lian Li 0002, Jingling Xue, Tin-Fook...
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
This paper considers the efficient parallel implementation of control constructs and expressions written in a common software programming language and synthesised to FPGA platform...
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
We are developing a cooking navigation system, which helps even a novice user to cook several recipes in parallel without failure, while improving an advanced user’s skill furth...
Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Sat...