2784 search results - page 264 / 557 » Instruction Level Parallelism |
145
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IPPS
1998
IEEE
15 years 8 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
112
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SPAA
1998
ACM
15 years 8 months ago
1998
ACM
We present a computation-centric theory of memory models. Unlike traditional processor-centric models, computation-centric models focus on the logical dependencies among instructi...
165
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HPCA
1996
IEEE
15 years 8 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
104
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IPPS
1996
IEEE
15 years 8 months ago
1996
IEEE
Virtual memory-mapped communication (VMMC) is a communication model providing direct data transfer between the sender's and receiver's virtual address spaces. This model...
147
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PPSN
1994
Springer
15 years 8 months ago
1994
Springer
This paper studies Genetic Programming (GP) and its relation to the Genetic Algorithm (GA). GP uses a GA approach to breed successive populations of programs, represented in the ch...