2784 search results - page 266 / 557 » Instruction Level Parallelism |
126
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CCGRID
2010
IEEE
15 years 2 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
119
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IEEECIT
2010
IEEE
15 years 2 months ago
2010
IEEE
—The relevance of instruction parallelization and optimal event scheduling is currently increasing. In particular, because of the high amount of computational power available tod...
140
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ICPP
2009
IEEE
15 years 1 months ago
2009
IEEE
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
133
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CORR
2011
Springer
14 years 11 months ago
2011
Springer
The memory consistency model is a fundamental system property characterizing a multiprocessor. The relative merits of strict versus relaxed memory models have been widely debated ...
145
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HPCA
2012
IEEE
13 years 11 months ago
2012
IEEE
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior propo...