2784 search results - page 275 / 557 » Instruction Level Parallelism |
158
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DATE
2010
IEEE
15 years 9 months ago
2010
IEEE
—Synchronous languages offer a deterministic model of concurrency at the level of actions. However, essentially all compilers for synchronous languages compile these actions into...
165
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EDOC
2000
IEEE
15 years 8 months ago
2000
IEEE
Software development in general and groupware applications in particular can greatly benefit from the reusability and interoperability aspects associated with software components....
120
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IPPS
1998
IEEE
15 years 8 months ago
1998
IEEE
List-based priority schedulers have long been one of the dominant classes of static scheduling algorithms. Such heuristics have been predominantly based around the "critical ...
116
Voted
HPCA
1997
IEEE
15 years 8 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
117
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HPCC
2007
Springer
15 years 7 months ago
2007
Springer
Efficient exploitation of the aggregate resources available to a researcher is a challenging and real problem. The challenge becomes all the greater when researchers who collaborat...