2784 search results - page 290 / 557 » Instruction Level Parallelism |
142
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IEEEPACT
2009
IEEE
15 years 1 months ago
2009
IEEE
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
143
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CCR
2010
15 years 1 months ago
2010
This paper presents iNFAnt, a parallel engine for regular expression pattern matching. In contrast with traditional approaches, iNFAnt adopts non-deterministic automata, allowing ...
130
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
127
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DAC
2006
ACM
16 years 4 months ago
2006
ACM
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
136
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CHI
2005
ACM
16 years 4 months ago
2005
ACM
Users of traditional tutorials and help systems often have difficulty finding the components described or pictured in the procedural instructions. Users also unintentionally miss ...