2784 search results - page 291 / 557 » Instruction Level Parallelism |
115
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ICCAD
2005
IEEE
16 years 22 days ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
124
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ICCAD
2001
IEEE
16 years 21 days ago
2001
IEEE
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
134
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SOSP
2007
ACM
16 years 21 days ago
2007
ACM
This paper describes an efficient and robust approach to provide a safe execution environment for an entire operating system, such as Linux, and all its applications. The approach...
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
—Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to ...
119
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ISCA
2007
IEEE
15 years 10 months ago
2007
IEEE
While Sequential Consistency (SC) is the most intuitive memory consistency model and the one most programmers likely assume, current multiprocessors do not support it. Instead, th...