2784 search results - page 301 / 557 » Instruction Level Parallelism |
113
Voted
HPCA
2006
IEEE
16 years 4 months ago
2006
IEEE
Hardware counters are a fundamental building block of modern high-performance processors. This paper explores two applications of probabilistic counter updates, in which the outpu...
101
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HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the h...
111
click to vote
HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
The issue logic of a superscalar processor dissipates a large amount of static and dynamic power. Furthermore, its power density makes it a hot-spot requiring expensive cooling sy...
138
Voted
HPCA
2005
IEEE
16 years 4 months ago
2005
IEEE
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
113
Voted
HPCA
2003
IEEE
16 years 4 months ago
2003
IEEE
To sustain instruction throughput rates in more aggressively clocked microarchitectures, microarchitects have incorporated larger and more complex branch predictors into their des...