Sciweavers

2784 search results - page 305 / 557
» Instruction Level Parallelism
Sort
View
133
Voted
WORDS
2002
IEEE
15 years 8 months ago
Writing Temporally Predictable Code
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
Peter P. Puschner, Alan Burns
EUROPAR
2001
Springer
15 years 8 months ago
Load Redundancy Elimination on Executable Code
Optimizations performed at link time or directly applied to nal program executables have received increased attention in recent years. This paper discuss the discovery and elimina...
Manel Fernández, Roger Espasa, Saumya K. De...
ISCA
1997
IEEE
120views Hardware» more  ISCA 1997»
15 years 8 months ago
Run-Time Adaptive Cache Hierarchy Management via Reference Analysis
Improvements in main memory speeds have not kept pace with increasing processor clock frequency and improved exploitation of instruction-level parallelism. Consequently, the gap b...
Teresa L. Johnson, Wen-mei W. Hwu
MICRO
1997
IEEE
76views Hardware» more  MICRO 1997»
15 years 8 months ago
A Framework for Balancing Control Flow and Predication
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
David I. August, Wen-mei W. Hwu, Scott A. Mahlke
PG
1997
IEEE
15 years 8 months ago
Real-time virtual humans
The last few years have seen great maturationin the computation speed and control methods needed to portray 3D virtualhumanssuitableforreal interactiveapplications. We first desc...
Norman I. Badler