2784 search results - page 306 / 557 » Instruction Level Parallelism |
113
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SIGGRAPH
1993
ACM
15 years 7 months ago
1993
ACM
A physically compact, low cost, high performance 3D graphics accelerator is presented. It supports shaded rendering of triangles and antialiased lines into a double-buffered 24-bi...
120
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DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
149
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AIPR
2008
IEEE
15 years 5 months ago
2008
IEEE
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
115
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ASPLOS
2008
ACM
15 years 5 months ago
2008
ACM
Many code analysis techniques for optimization, debugging, or parallelization need to perform runtime disambiguation of sets of addresses. Such operations can be supported efficie...
122
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DAC
2005
ACM
15 years 5 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...