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» Instruction Level Parallelism
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144
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CODES
2008
IEEE
15 years 5 months ago
Software optimization for MPSoC: a mpeg-2 decoder case study
Using traditional software profiling to optimize embedded software in an MPSoC design is not reliable. With multiple processors running concurrently and programs interacting, trad...
Eric Cheung, Harry Hsieh, Felice Balarin
135
Voted
ISCAPDCS
2004
15 years 5 months ago
An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs
Hyperthreaded(HT) and simultaneous multithreaded (SMT) processors are now available in commodity workstations and servers. This technology is designed to increase throughput by ex...
Yun Zhang, Mihai Burcea, Victor Cheng, Ron Ho, Mic...
117
Voted
CGF
2008
121views more  CGF 2008»
15 years 3 months ago
Knitting a 3D Model
A knitted animal is made of a closed surface consisting of several knitted patches knitted out of yarn and stuffed with cotton (Fig. 1). We introduce a system to create a knitting...
Yuki Igarashi, Takeo Igarashi, Hiromasa Suzuki
136
Voted
COMPUTER
1998
94views more  COMPUTER 1998»
15 years 3 months ago
Multiprocessors Should Support Simple Memory-Consistency Models
provide tools or abstractions that allow developers to program in parallel. But what hardware do we need to support shared memory threads? The hardware should provide a well-defin...
Mark D. Hill
116
Voted
MICRO
2002
IEEE
121views Hardware» more  MICRO 2002»
15 years 3 months ago
Convergent scheduling
Convergent scheduling is a general framework for instruction scheduling and cluster assignment for parallel, clustered architectures. A convergent scheduler is composed of many ind...
Walter Lee, Diego Puppin, Shane Swenson, Saman P. ...