2784 search results - page 310 / 557 » Instruction Level Parallelism |
114
Voted
IPPS
1998
IEEE
15 years 8 months ago
1998
IEEE
Abstract. The nano-threads programming model was proposed to effectively integrate multiprogramming on shared-memory multiprocessors, with the exploitation of fine-grain parallelis...
151
Voted
WCET
2010
15 years 1 months ago
2010
To take full advantage of the increasingly used shared-memory multicore architectures, software algorithms will need to be parallelized over multiple threads. This means that thre...
145
Voted
HPCA
2009
IEEE
16 years 4 months ago
2009
IEEE
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
168
Voted
IWOMP
2007
Springer
15 years 9 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
122
Voted
MIDDLEWARE
2005
Springer
15 years 9 months ago
2005
Springer
This paper outlines the benefits of adopting serviceoriented architectures at the level of communications between resource-constrained embedded devices, in particular for industri...