2784 search results - page 322 / 557 » Instruction Level Parallelism |
134
Voted
JSSPP
2010
Springer
15 years 1 months ago
2010
Springer
Many computational solutions can be expressed as directed acyclic graphs (DAGs) with weighted nodes. In parallel computing, scheduling such DAGs onto manycore processors remains a ...
134
Voted
HPDC
1996
IEEE
15 years 7 months ago
1996
IEEE
' The coming of giga-bit networks makes possible the realization ofa single nationwide virtual computer comprised of a variety of geographically distributed highpe6ormance mac...
144
Voted
DAC
2002
ACM
16 years 4 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
139
Voted
PIMRC
2008
IEEE
15 years 10 months ago
2008
IEEE
—Highways are an essential component of our society because they are critical to quality of life and to local and national economies. Under good conditions, highways provide a sa...
132
Voted
DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
Cutting-edge applications of future embedded systems demand highest processor performance with low power consumption to get acceptable battery-life times. Therefore, low power opt...