2784 search results - page 323 / 557 » Instruction Level Parallelism |
167
Voted
ACMMSP
2006
ACM
15 years 9 months ago
2006
ACM
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....
128
Voted
ICALT
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper we present an architecture dedicated to an intelligently assisted educational tool which integrates within a unified framework software rational agents both at the m...
256
Voted
EH
1999
IEEE
1999
IEEE
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
15 years 8 months ago
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
118
Voted
CASES
2008
ACM
15 years 5 months ago
2008
ACM
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
136
Voted
EUROPAR
2006
Springer
15 years 7 months ago
2006
Springer
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...