Sciweavers

2784 search results - page 326 / 557
» Instruction Level Parallelism
Sort
View
137
Voted
IPPS
2006
IEEE
15 years 9 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
IPPS
2006
IEEE
15 years 9 months ago
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems
High-performance multiprocessor systems built around out-of-order processors with aggressive branch predictors execute many memory references that turn out to be on a mispredicted...
Resit Sendag, Ayse Yilmazer, Joshua J. Yi, Augustu...
133
Voted
IPPS
2006
IEEE
15 years 9 months ago
Compatible phase co-scheduling on a CMP of multi-threaded processors
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya...
113
Voted
IPPS
2005
IEEE
15 years 9 months ago
A Dependency Chain Clustered Microarchitecture
In this paper we explore a new clustering approach for reducing the complexity of wide issue in-order processors based on EPIC architectures. Complexity effectiveness is achieved ...
Satish Narayanasamy, Hong Wang 0003, Perry H. Wang...
143
Voted
IPPS
2005
IEEE
15 years 9 months ago
An Empirical Study On the Vectorization of Multimedia Applications for Multimedia Extensions
Multimedia extensions (MME) are architectural extensions to general-purpose processors to boost the performance of multimedia workloads. Today, in-line assembly code, intrinsic fu...
Gang Ren, Peng Wu, David A. Padua