Sciweavers

2784 search results - page 328 / 557
» Instruction Level Parallelism
Sort
View
171
Voted
ICDCS
1999
IEEE
15 years 8 months ago
HiFi: A New Monitoring Architecture for Distributed Systems Management
With the increasing complexity of large-scale distributed (LSD) systems, an efficient monitoring mechanism has become an essential service for improving the performance and reliab...
Ehab S. Al-Shaer, Hussein M. Abdel-Wahab, Kurt Mal...
127
Voted
HIPC
1999
Springer
15 years 8 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller
152
Voted
ISHPC
1999
Springer
15 years 8 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
147
Voted
CASES
2007
ACM
15 years 7 months ago
Hierarchical coarse-grained stream compilation for software defined radio
Software Defined Radio (SDR) is an emerging embedded domain where the physical layer of wireless protocols is implemented in software rather than the traditional application speci...
Yuan Lin, Manjunath Kudlur, Scott A. Mahlke, Trevo...
124
Voted
ICS
2000
Tsinghua U.
15 years 7 months ago
Using complete system simulation to characterize SPECjvm98 benchmarks
Complete system simulation to understand the influence of architecture and operating systems on application execution has been identified to be crucial for systems design. While t...
Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan,...