2784 search results - page 360 / 557 » Instruction Level Parallelism |
153
Voted
IPPS
2010
IEEE
15 years 22 days ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
158
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HPCA
2012
IEEE
13 years 11 months ago
2012
IEEE
The least recently used (LRU) replacement policy performs poorly in the last-level cache (LLC) because temporal locality of memory accesses is filtered by first and second level...
105
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ASAP
2008
IEEE
15 years 10 months ago
2008
IEEE
Data movement operations, such as the C-style memcpy function, are often used to duplicate or communicate data. This type of function typically produces a significant amount of o...
124
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
115
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ISORC
2008
IEEE
15 years 10 months ago
2008
IEEE
The specific constraints that must be satisfied by embedded systems, such as timeliness, energy efficiency of battery-operated devices, dependable operation in safety-relevant sce...