2784 search results - page 378 / 557 » Instruction Level Parallelism |
129
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IPSN
2007
Springer
15 years 9 months ago
2007
Springer
Many sensor nodes contain resource constrained microcontrollers where user level applications, operating system components, and device drivers share a single address space with no...
117
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VLSI
2007
Springer
15 years 9 months ago
2007
Springer
In this paper, we present the way of fast and accurate estimation of software energy consumption in off-the-shelf processor using IPI(Inter-Prefetch Interval) energy model. In ou...
140
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ISCA
2006
IEEE
15 years 9 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
115
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ACSAC
2005
IEEE
15 years 9 months ago
2005
IEEE
Microscopic analysis of malicious code (malware) requires the aid of a variety of powerful tools. Chief among them is a debugger that enables runtime binary analysis at an instruc...
158
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...