2784 search results - page 381 / 557 » Instruction Level Parallelism |
117
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ISCA
2000
IEEE
15 years 7 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
131
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ISCA
2000
IEEE
15 years 7 months ago
2000
IEEE
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
104
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ASPDAC
2000
ACM
15 years 7 months ago
2000
ACM
Reducing power consumption has become a key goal for systemon-a-chip (SOC) designs. Fast and accurate power estimation is needed early in the design process, since power reduction...
116
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DAC
1999
ACM
15 years 7 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
173
Voted
CADE
1998
Springer
15 years 7 months ago
1998
Springer
Abstract. We present the first implementation of a theorem prover running on a smart card. The prover is written in Java and implements a dual tableau calculus. Due to the limited ...