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147
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JUCS
2000
120views more  JUCS 2000»
15 years 3 months ago
Execution and Cache Performance of the Scheduled Dataflow Architecture
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
Krishna M. Kavi, Joseph Arul, Roberto Giorgi
115
Voted
JOCN
2010
71views more  JOCN 2010»
15 years 1 months ago
Mechanisms and Dynamics of Cortical Motor Inhibition in the Stop-signal Paradigm: A TMS Study
■ The ability to stop ongoing motor responses in a splitsecond is a vital element of human cognitive control and flexibility that relies in large part on prefrontal cortex. We u...
Wery P. M. van den Wildenberg, Borís Burle,...
ACSAC
2010
IEEE
15 years 4 days ago
Heap Taichi: exploiting memory allocation granularity in heap-spraying attacks
Heap spraying is an attack technique commonly used in hijacking browsers to download and execute malicious code. In this attack, attackers first fill a large portion of the victim...
Yu Ding, Tao Wei, Tielei Wang, Zhenkai Liang, Wei ...
210
Voted
SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
14 years 10 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
JIPS
2010
138views more  JIPS 2010»
14 years 10 months ago
A Study on Design and Implementation of the Ubiquitous Computing Environment-based Dynamic Smart On/Off-line Learner Tracking Sy
In order to provide a tailored education for learners within the ubiquitous environment, it is critical to undertake an analysis of the learning activities of learners. For this pu...
Hyung-Min Lim, Kun-Won Jang, Byung-Gi Kim