2784 search results - page 387 / 557 » Instruction Level Parallelism |
120
Voted
HPCA
2008
IEEE
16 years 3 months ago
2008
IEEE
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
124
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HPCA
2007
IEEE
16 years 3 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
190
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HPCA
2004
IEEE
16 years 3 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
123
Voted
ASPLOS
2010
ACM
15 years 10 months ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
131
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ASPLOS
2010
ACM
15 years 10 months ago
2010
ACM
SIMD (Single Instruction, Multiple Data) engines are an essential part of the processors in various computing markets, from servers to the embedded domain. Although SIMD-enabled a...