2784 search results - page 388 / 557 » Instruction Level Parallelism |
130
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IEEEPACT
2008
IEEE
15 years 9 months ago
2008
IEEE
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
121
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PLDI
2005
ACM
15 years 9 months ago
2005
ACM
Modulo scheduling is an effective code generation technique that exploits the parallelism in program loops by overlapping iterations. One drawback of this optimization is that reg...
140
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VEE
2005
ACM
15 years 9 months ago
2005
ACM
Modern transactional response-time sensitive applications have run into practical limits on the size of garbage collected heaps. The heap can only grow until GC pauses exceed the ...
121
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ICS
2005
Tsinghua U.
15 years 9 months ago
2005
Tsinghua U.
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
150
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ICS
2005
Tsinghua U.
15 years 9 months ago
2005
Tsinghua U.
Supercomputer architects strive to maximize the performance of scientific applications. Unfortunately, the large, unwieldy nature of most scientific applications has lead to the...