2784 search results - page 390 / 557 » Instruction Level Parallelism |
165
click to vote
JMM2
2006
15 years 3 months ago
2006
Abstract-- This paper describes a framework for constructing a three-dimensional immersive environment that can be used for training physical activities. The system is designed to ...
125
click to vote
JSA
2000
15 years 3 months ago
2000
Integrating processors and main memory is a promising approach to increase system performance. Such integration provides very high memory bandwidth that can be exploited efficientl...
157
Voted
MICRO
2010
IEEE
15 years 1 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
183
Voted
OOPSLA
2010
Springer
15 years 1 months ago
2010
Springer
Heterogeneous multi-core processors, such as the IBM Cell processor, can deliver high performance. However, these processors are notoriously difficult to program: different cores...
136
Voted
HPDC
2006
IEEE
15 years 9 months ago
2006
IEEE
Consider a workload in which massively parallel tasks that require large resource pools are interleaved with short tasks that require fast response but consume fewer resources. We...