2784 search results - page 401 / 557 » Instruction Level Parallelism |
110
Voted
DAC
2009
ACM
16 years 4 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...
115
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SPAA
2009
ACM
16 years 3 months ago
2009
ACM
This workshop paper reports work in progress on NZTM, a nonblocking, zero-indirection object-based hybrid transactional memory system. NZTM can execute transactions using best-eff...
186
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HPCA
2003
IEEE
16 years 3 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
201
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SIGMOD
2009
ACM
16 years 3 months ago
2009
ACM
The ParAccel Analytic DatabaseTM is a fast shared-nothing parallel relational database system with a columnar orientation, adaptive compression, memory-centric design, and an enha...
112
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PPOPP
2010
ACM
16 years 16 days ago
2010
ACM
We propose a concurrent relaxed balance AVL tree algorithm that is fast, scales well, and tolerates contention. It is based on optimistic techniques adapted from software transact...