2784 search results - page 402 / 557 » Instruction Level Parallelism |
114
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ICCAD
2001
IEEE
16 years 5 days ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
148
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PDP
2010
IEEE
15 years 10 months ago
2010
IEEE
—It is clear that Cloud computing is and will be a sea change for the Information Technology by changing the way in which both software and hardware are designed and purchased. I...
125
Voted
ICDCS
2009
IEEE
15 years 10 months ago
2009
IEEE
The usage of network resources by content providers is commonly governed by Service Level Agreements (SLA) between the content provider and the network service provider. Resource ...
109
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FASE
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. E-government services usually process large amounts of confidential data. Therefore, security requirements for the communication between components have to be adhered in...
126
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ICS
2009
Tsinghua U.
15 years 10 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...