2784 search results - page 422 / 557 » Instruction Level Parallelism |
132
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IPPS
2000
IEEE
15 years 7 months ago
2000
IEEE
The switch design for interconnection networks plays an important role in the overall performance of multiprocessors and computer networks. It is therefore crucial to study variou...
121
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IPPS
2000
IEEE
15 years 7 months ago
2000
IEEE
Only a handful of fundamental mechanisms for synchronizing the access of concurrent threads to shared memory are widely implemented and used. These include locks, condition variab...
134
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SC
2000
ACM
15 years 7 months ago
2000
ACM
This paper describes performance tuning experiences with a three-dimensional unstructured grid Euler flow code from NASA, which we have reimplemented in the PETSc framework and p...
136
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HCW
1999
IEEE
15 years 7 months ago
1999
IEEE
A major challenge in Metacomputing Systems (Computational Grids) is to effectively use their shared resources, such as compute cycles, memory, communication network, and data repo...
122
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HPCA
1999
IEEE
15 years 7 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...