2784 search results - page 448 / 557 » Instruction Level Parallelism |
102
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ISCAS
1993
IEEE
15 years 7 months ago
1993
IEEE
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
170
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AHS
2006
IEEE
15 years 6 months ago
2006
IEEE
We propose a novel type of dynamically reconfigurable System-on-Chip architecture, the Gannet service-based architecture. This novel concept addresses the issue of systemlevel rec...
119
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ASPDAC
1995
ACM
15 years 6 months ago
1995
ACM
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
112
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ICCAD
1991
IEEE
15 years 6 months ago
1991
IEEE
In a high level synthesis environment there is a strong need for flexible module generators. For the generation of regular structures efficient dedicated module generators can be ...
131
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ACL
2008
15 years 4 months ago
2008
We propose using large-scale clustering of dependency relations between verbs and multiword nouns (MNs) to construct a gazetteer for named entity recognition (NER). Since dependen...