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ICECCS
2010
IEEE
196views Hardware» more  ICECCS 2010»
15 years 1 months ago
Implementing and Evaluating a Model Checker for Transactional Memory Systems
Abstract—Transactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM ...
Woongki Baek, Nathan Grasso Bronson, Christos Kozy...
IJHPCA
2007
114views more  IJHPCA 2007»
15 years 23 days ago
An Approach To Data Distributions in Chapel
A key characteristic of today’s high performance computing systems is a physically distributed memory, which makes the efficient management of locality essential for taking adv...
R. E. Diaconescu, Hans P. Zima
113
Voted
ISCA
2007
IEEE
94views Hardware» more  ISCA 2007»
15 years 22 days ago
Tailoring quantum architectures to implementation style: a quantum computer for mobile and persistent qubits
In recent years, quantum computing (QC) research has moved from the realm of theoretical physics and mathematics into real implementations [9]. With many different potential hardw...
Eric Chi, Stephen A. Lyon, Margaret Martonosi
126
Voted
PC
2007
161views Management» more  PC 2007»
15 years 10 days ago
High performance combinatorial algorithm design on the Cell Broadband Engine processor
The Sony–Toshiba–IBM Cell Broadband Engine (Cell/B.E.) is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD co-process...
David A. Bader, Virat Agarwal, Kamesh Madduri, Seu...
111
Voted
IPPS
2010
IEEE
14 years 10 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...