This paper presents a performance analysis of an accelerated 2-D rigid image registration implementation that employs the Compute Unified Device Architecture (CUDA) programming e...
The fine-grained parallelism inherent in FPGAs has encouraged their use in packet processing systems. Debugging and performance evaluation of such complex designs can be signifi...
Paul Edward McKechnie, Michaela Blott, Wim Vanderb...
—The design of an Enterprise Architecture (EA) management function for an enterprise is no easy task. Various frameworks exist as well as EA management tools, which promise to de...
Sabine Buckl, Alexander M. Ernst, Florian Matthes,...
Long running High Performance Computing (HPC) applications at scale must be able to tolerate inevitable faults if they are to harness current and future HPC systems. Message Passi...
Broadcast of information in wireless sensor networks is an important operation, e.g., for code updates, queries, membership information, etc. In this paper, we analyze and experim...