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FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 6 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
114
Voted
HIPC
2003
Springer
15 years 6 months ago
Dynamic Load Balancing for I/O-Intensive Tasks on Heterogeneous Clusters
1 Since I/O-intensive tasks running on a heterogeneous cluster need a highly effective usage of global I/O resources, previous CPUor memory-centric load balancing schemes suffer ...
Xiao Qin, Hong Jiang, Yifeng Zhu, David R. Swanson
GPC
2010
Springer
15 years 5 months ago
SLA-Driven Automatic Bottleneck Detection and Resolution for Read Intensive Multi-tier Applications Hosted on a Cloud
Abstract. A Service-Level Agreement (SLA) provides surety for specific quality attributes to the consumers of services. However, the current SLAs offered by cloud providers do no...
Waheed Iqbal, Matthew N. Dailey, David Carrera, Pa...
DATE
2010
IEEE
153views Hardware» more  DATE 2010»
15 years 5 months ago
HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling
— This paper describes a Model Order Reduction algorithm for multi-dimensional parameterized systems, based on a sampling procedure which incorporates a low order moment matching...
Jorge Fernandez Villena, Luis Miguel Silveira
104
Voted
DSD
2002
IEEE
110views Hardware» more  DSD 2002»
15 years 5 months ago
A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
Shoji Goto, Takashi Yamada, Norihisa Takayarna, Yo...