2784 search results - page 494 / 557 » Instruction Level Parallelism |
120
click to vote
CHES
2004
Springer
15 years 6 months ago
2004
Springer
Abstract. Recently, Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of F p6 with order dividing p2 -p+1 by their trace over Fp2 ....
137
click to vote
ARCS
2006
Springer
15 years 6 months ago
2006
Springer
Early energy estimation is increasingly important in MultiProcessor System-On-Chip (MPSoC) design. Applying traditional approaches, which consist in delaying the estimation until t...
126
click to vote
ASPLOS
2006
ACM
15 years 6 months ago
2006
ACM
Debugging data races in parallel applications is a difficult task. Error-causing data races may appear to vanish due to changes in an application's optimization level, thread...
126
click to vote
EMSOFT
2006
Springer
15 years 6 months ago
2006
Springer
We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the la...
125
click to vote
ATS
2001
IEEE
15 years 6 months ago
2001
IEEE
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...