2784 search results - page 80 / 557 » Instruction Level Parallelism |
MICRO
1992
IEEE
15 years 4 months ago
1992
IEEE
- We present a compilation technique for scheduling parallelism on fine grained asynchronous MIMD systems. The shape scheduling algorithm is introduced that utilizes the flexibilit...
ICIP
2007
IEEE
16 years 1 months ago
2007
IEEE
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...
101
click to vote
ASPDAC
2005
ACM
15 years 1 months ago
2005
ACM
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
106
click to vote
CODES
2007
IEEE
15 years 6 months ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
HPCA
2005
IEEE
16 years 8 days ago
2005
IEEE
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...