2784 search results - page 81 / 557 » Instruction Level Parallelism |
IEEEPACT
2007
IEEE
15 years 6 months ago
2007
IEEE
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
ISCA
2002
IEEE
15 years 4 months ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
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SPAA
2006
ACM
15 years 5 months ago
2006
ACM
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or eve...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
MICRO
2000
IEEE
15 years 4 months ago
2000
IEEE
Virtual machine service threads can perform many tasks in parallel with program execution such as garbage collection, dynamic compilation, and profile collection and analysis. Har...