2784 search results - page 82 / 557 » Instruction Level Parallelism |
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
AES
2000
Springer
15 years 4 months ago
2000
Springer
We compare the five candidates for the Advanced Encryption Standard based on their performance on the Alpha 21264, a 64-bit superscalar processor. There are several new features o...
ISHPC
2000
Springer
15 years 3 months ago
2000
Springer
Deeply pipelined high performance processors require highly accurate branch prediction to drive their instruction fetch. However there remains a class of events which are not easi...
IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
PPAM
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. We address parallel jobs scheduling problem for computational GRID systems. We concentrate on two-level hierarchy scheduling: at the first level broker allocates computa...