Sciweavers

2784 search results - page 84 / 557
» Instruction Level Parallelism
Sort
View
DATE
2002
IEEE
137views Hardware» more  DATE 2002»
15 years 4 months ago
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
Qin Zhao, Bart Mesman, Twan Basten
ASSETS
2008
ACM
15 years 1 months ago
American sign language vocabulary: computer aided instruction for non-signers
In this paper we present the results of a study designed to evaluate the computer-based methods of learning American Sign Language (ASL). We describe a method including an initial...
Valerie Henderson-Summet, Kimberly Weaver, Tracy L...
SASP
2009
IEEE
222views Hardware» more  SASP 2009»
15 years 6 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
15 years 3 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
IEEEPACT
2006
IEEE
15 years 6 months ago
Branch predictor guided instruction decoding
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
Oliverio J. Santana, Ayose Falcón, Alex Ram...