2784 search results - page 87 / 557 » Instruction Level Parallelism |
138
click to vote
ISSS
1996
IEEE
15 years 4 months ago
1996
IEEE
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
103
click to vote
IJSI
2008
14 years 12 months ago
2008
In this paper, we demonstrate the use of qualitative spatial modelling as the foundation for the conceptual representation of route instructions, to enable robust humanrobot intera...
HPCA
2008
IEEE
15 years 6 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
104
click to vote
ISORC
2005
IEEE
15 years 5 months ago
2005
IEEE
Heuristic algorithms have enjoyed increasing interests and success in the context of Utility Accrual (UA) scheduling. However, few analytical results, such as bounds on task-level...
118
click to vote
HIPC
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. Linear scan register allocation is an attractive register allocation algorithm because of its simplicity and fast running time. However, it is generally felt that linear ...