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EUROPAR
2001
Springer
15 years 4 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
EUC
2006
Springer
15 years 3 months ago
Saving Register-File Leakage Power by Monitoring Instruction Sequence in ROB
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
Wann-Yun Shieh, Hsin-Dar Chen
SAMOS
2010
Springer
14 years 9 months ago
OpenCL-based design methodology for application-specific processors
OpenCL is a programming language standard which enables the programmer to express the application by structuring its computation as kernels. The OpenCL compiler is given the explic...
Pekka O. Jaskelainen, Carlos S. de La Lama, Pablo ...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
16 years 8 days ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
IPPS
1994
IEEE
15 years 4 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...