2784 search results - page 90 / 557 » Instruction Level Parallelism |
HUC
2010
Springer
15 years 2 days ago
2010
Springer
We present a study that evaluates the effectiveness of augmenting on-screen instructions with micro-projection for manual task guidance unlike prior work, which replaced screen in...
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LCTRTS
2007
Springer
15 years 6 months ago
2007
Springer
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
ICASSP
2011
IEEE
14 years 3 months ago
2011
IEEE
Parallel computation of the adaptive lattice filtering algorithm is difficult due to the dependency problem caused by feedback operations. The conventional control-level paralle...
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
IEEEPACT
2006
IEEE
15 years 6 months ago
2006
IEEE
Modern compiler transformations that eliminate redundant computations or reorder instructions, such as partial redundancy elimination and instruction scheduling, are very effectiv...